Logic network for programmable data concentrator

Abstract

For the selective energization of combinations of up to m data outputs of a data concentrator with n data inputs (n > m), the concentrator is provided with n control inputs energizable in various patterns. The concentrator comprises a logic network with an enabling section and a performing section, each in the form of a truncated orthogonal matrix with m rows and n columns of gating circuits. In each matrix the number of gating circuits decreases from n in the first row to (n-m+1) in the last row. The gating circuits of each column of the enabling matrix are connected in parallel to a respective control input whose energization gives rise to an internal activation signal in one of these circuits and simultaneously blocks the circuits of the same row while unblocking those on a diagonal for possible activation by the energization of one of the following control inputs; thus, only one activation signal can come from any row and the number of such activation signals -- up to m -- depends on the number of energized control inputs. The gating circuits of the performing section consist each of a coincidence (NAND or AND) gate connected on the one hand to an output terminal of the corresponding circuit of the enabling matrix and on the other hand to a data input, the gates of each column being connected to the same data input in parallel; the gates of each row work into a common summing circuit (NAND or OR gate) energizing a respective data output if an activation signal is applied to a gating circuit of that row connected to an energized data input.