The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 1977

Filed:

Mar. 26, 1975
Applicant:
Inventors:

Garvin Wesley Patterson, Glendale, AZ (US);

William A Shelly, Phoenix, AZ (US);

Jaime Calle, Glendale, AZ (US);

Earnest M Monahan, Phoenix, AZ (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
3401725 ;
Abstract

An input/output data processing system includes a plurality of active modules, a plurality of passive modules and at least one memory module and a system interface unit having a plurality of ports, each of which connect to a different one of the modules. Each module connects to one of the ports by a plurality of different interfaces. The active modules include an input/output processing unit for processing interrupts and executing command sequences and a multiplexer unit for directly controlling transfers between the memory module and any one of the peripheral devices coupled to different ones of a plurality of ports of the multiplexer unit. Different ones of the modules of the system include the programmable interface used for transferring command information to the multiplexer unit and to the devices associated therewith for enabling a different type of control to proceed in parallel with input/output data transfer operations. Each multiplexer unit includes a plurality of storage registers which are operatively coupled to the programmable interface associated therewith for receiving control information therefrom designating the priority to be given by the unit to the processing of different types of interrupt signals received from devices associated therewith in addition to information designating which one of a set of processing routines to be used in servicing the interrupt.


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