The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 1977
Filed:
Dec. 19, 1974
Nicolaas Alphonsus Verhoeckx, Emmasingel, NL;
Herman VAN DER Hoff, Hilversum, NL;
Cornelis Henricus Vos, Emmasingel, NL;
Johannes Wilhelmus Coenders, Emmasingel, NL;
U.S. Philips Corporation, New York, NY (US);
Abstract
In a videophone system sound, video, synchronizing and signalling signals are to be transmitted through a single pair of telephone cables of existing telephone communications. In that case sound, synchronizing and signalling signals are transmitted in a digital form and the video signals are transmitted in an analog form. It is then possible to achieve optimum picture quality at the given bandwidth of the existing telephone communications. If for the given bandwidth the video signal were also digitalized, this would be at the expense of the picture quality. However, it is then necessary to transmit information regarding clock pulses for decoding at the receiver end. To be able to synchronize at the receiver end only on two frequencies instead of on clock pulse frequency, line frequency and field frequency, the information regarding the clock pulses is cotransmitted in such a manner that a clock pulse generator at the receiver end can be synchronized therewith which generator supplies clock pulses. A field code word is also transmitted during each field flyback period. In the receiver the regenerated clock pulses are divided in frequency in a divider stage and the divided signal is compared with the detected code word in a synchronizing verification circuit. As long as there is no phase equality between component signals and detected code word, an output signal from the verification circuit resets the divider stage.