The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 18, 1977
Filed:
Nov. 03, 1975
Yasuki Rai, Kyoto, JA;
Terutoshi Sasami, Osaka, JA;
Yuzuru Hasegawa, Osaka, JA;
Masaru Okazoe, Osaka, JA;
Sanyo Electric Co., Ltd., Moriguchi, JA;
Abstract
A semiconductor memory device comprising a composite structure of semiconductor-insulation layer-floating gate-insulation layer-control gate, in which a periphery of said floating gate is formed to extend up to and immediately above at least one of source and drain regions, such that both overlap each other through the insulation layer therebetween of silicon dioxide and of a thickness of 200 to 400A for more than 0.35 microns in length but not exceeding two times the distance between the source and drain regions. In erasing the contents written in the inventive memory device, a voltage is applied between the substrate and at least one of the source and drain regions in a reverse bias direction with respect to a junction therebetween, while the control gate is supplied with the same potential as that of the substrate or grounded, said erasing voltage being selected to a relatively small value sufficient to cause a Fowler-Nordheim tunnel phenomenon through the first insulation layer between the floating gate and at least one of the source and drain regions at said overlapping area.