The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 21, 1976
Filed:
Apr. 19, 1974
William Bogan Archey, Shelburne, VT (US);
Ronald Dominic Audi, Burlington, VT (US);
Roger James Clark, Underhill, VT (US);
Robert James Redmond, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A liquid encapsulated high density integrated circuit package which serves as a complete computer basic system module having both logic and memory circuits in the same package. This unit takes advantage of improvements in the integrated circuit art to minimize the number of physical units required to provide the desired memory capacity while simultaneously maximizing density and thereby minimizing signal path length. Basically the package contains a plurality of stacked semiconductor wafers each of which provides either integrated memory or logic functions. Each semiconductor wafer is mounted on an insulated wafer carrier and is connected to stacking pins around the perimeter of the carrier via a series of radial interconnection which are flexible expansion leads disposed around the outer edge of the wafer. Each wafer is floatation mounted by attaching only its center to the carrier to minimize the stress effects of a thermal expansion mismatch between the wafer, the carrier, and the radial interconnections. The carrier on which the wafer is mounted is constructed to mechanically secure and support the wafer at its physical center, to provide electrical contact to the wafer substrate, to provide support of electrical stacking pins which connect with stacking pins on adjacent carriers, to provide support for the radial interconnection expansion leads extending between pads on the wafer and the stacking pins and to minimize the effects of thermal mismatch in the structure. A finned housing encloses the stacked wafers and carriers and is hermetically sealed to a header having feed through termination pin such that the package can contain a liquid coolant which aids in the transfer of heat between the wafers and the finned housing thus maximizing the dissipation of heat from the wafers.