Error logging in semiconductor storage units

Abstract

A maintenance procedure comprising a method of and an apparatus for storing information identifying the location of one or more defective bits, i.e., a defective memory element, a defective storage device or a failure, in a single-error-correcting semiconductor main storage unit (MSU) comprised of a plurality of large scale integrated (LSI) bit planes. The method utilizes an error logging store (ELS) comprised of 128 word-group-associated memory registers, each memory register storing 1 tag bit and 6 syndrome bits. Upon determination of a single bit error during the readout of a word from the MSU, stored in the ELS are: (1) a tag bit that when set signifies that a defective bit has been determined to be in the one associated word group; and, (2) a group of 6 syndrome bits that identifies that one of the 45, 1024-bit planes of the one associated word group that contains the defective bit. A defective device counter (DDC) counts the set tag bits in the ELS and is utilized by the machine operator to schedule preventative maintenance of the MSU by replacing the defective bit planes. By statistically determining the number of allowable failures, i.e., the number of correctable failures that may occur before the expected occurrence of a noncorrectable double bit error, preventative maintenance may be scheduled only as required by the particular MSU.