Depletion mode field effect transistor memory system

Abstract

The present invention relates to an integrated memory system comprising an array of depletion mode field effect transistors operated in a common control electrode mode to provide an array with the density of metal oxide semiconductor field effect transistor arrays and the speed of bipolar transistor arrays. Each transistor of the array has a gate or control electrode surrounding a channel region of the device which gate is held at a reference potential with respect to the source and drain regions which are selectively biased. The invention can be utilized in both a random access memory and a read only memory mode. The read only mode is somewhat of a simpler structure capable of a higher density than that of the random access. In both cases a low capacity, high density, high speed memory which is self limiting as to current and which uses a lower power requirement than comparable Bipolar memories is realized. The field effect transistors of the invention are readily formed using existing processes that will permit bipolar devices to be made on the same chip.