Serial pulse-code-modulated retiming system

Abstract

An improved clock retiming system for pulse coded data is provided in which the clock signals are extracted from the encoded data and first and second signals of the same amplitude and frequency but of different phase are generated from the clock signals. First and second amplifiers having variable gains provide amplification for the first and second signals, respectively. The first and second amplified signals are summed to produce a third signal having a phase which is a function of the relative amplitudes of the first and second amplified signals. The original pulse encoded data is sampled with the third signal to produce the retimed data output. The original pulse encoded data is also utilized to sample the third signal. The resulting signal is filtered to provide a DC voltage feedback error signal indicative of the phase difference between the third signal and the original pulse encoded data. This feedback signal is translated into a pair of complementary signals forming inputs to the first and second amplifiers, respectively, to vary the variable gains thereof, oppositely thereby adjusting the phase of the third signal to correspond to the phase of the original pulse encoded data.