Integrated semiconductor circuit master-slice structure in which the

Abstract

A planar integrated semiconductor circuit master-slice structure in which the insulation layer over the planar surface remains intact and free of undesirable short-circuit paths in the area beneath excess 'unused' contact terminals which are not part of the selected circuit configuration formed by a selected surface metallization pattern on the insulative layer which selectively interconnects less than all of the contact terminals with less than all of the components extending from the planar surface of a semiconductor substrate beneath the insulative layer. During D.C. sputter cleaning or etching utilized in the formation of the contact terminals and the metallization pattern, there is an undesirable charge accumulation on the unused contact terminals which tends to exceed the dielectric breakdown strength of the insulative layer beneath the terminal. This shorts the unused pad to the semiconductor substrate beneath the terminal. Such short-circuits are avoided by an additional metallization line, not part of the circuit configuration, which connects the unused contact terminal to an unused electrically isolated component e.g. junction isolated component in the semiconductor substrate.