Multilayer insulation integrated circuit structure

Abstract

A planar semiconductor integrated circuit chip structure containing a planar surface from which a plurality of regions of different types and concentrations of conductivity-determining impurities extends into the chip to provide the active and passive devices of the circuit. The surface is passivated with an insulative structure containing at least two layers with a metallization pattern for interconnecting the integrated circuit devices formed on the first layer and via holes passing through the second or upper layer into contact with various portions of this metallization pattern. The via holes are arranged so that a majority of the holes are disposed above surface regions having such impurity types and concentrations that would form Schottky barrier contacts with the metal of contacts formed in said via holes. Accordingly, if during the formation of the via holes by etching through the second layer, there is an attendant further etching through the first layer to the surface of a semiconductor region, said region will form a Schottky barrier contact with the metal deposited in the via holes, which contact will act to prevent a short circuit between the metallization and the surface region.