Programmable logic controller with flag storage

Abstract

A programmable logic controller has input elements sampled to determine status in each of multicomponent lines of a relay ladder network. Output elements in the network connect power voltage sources to power utilization units and disconnect the same in accordance with a programmed set of instructions stored in a controller memory to satisfy operating conditions required of the ladder network. Sample means sequentially generate a set of one bit words, one word representing the state of each of the input elements. A set of one bit output control states is generated, one state for each output element in dependence upon the states of the input elements. Timing means operable once each half cycle of the power voltage initiates generation and storage in a semiconductor read/write image register of one bit input words and output control states. Further, the timing means includes control means for sequentially instituting a serial I/O mode in which the input elements are sampled and the output states are read out of the register and applied to the output elements followed by a run mode in which a new set of control states is established and stored in the register.