Phase lock loop with delay circuits for relative digital decoding over a

Abstract

In a feedback control system wherein data pulses also establish timing coordination between the data and the processing devices, two delay circuits are provided to extract the synchronized clock pulses from the coded incoming signal. This enables relative digital decoding and ensures a precise data transfer to a computer interface. One of the delay circuits enables a data reconditioner circuit to buffer the data and eliminates data peak shifting. The reconditioned data is provided to a coincident circuit which selectively transfers the data to a computer interface and to a phase difference detector. The other delay circuit provides to the phase difference detector a second input corresponding in time to the coded incoming data pulses. The detector's output generates a DC error voltage which synchronizes a voltage controlled oscillator (VCO). The outputs of the VCO are clock pulses in phase with the coded incoming signals. The feedback control system is capable of operating over a range of frequencies without effecting the margin for peak shifting.