Automatic channel assignment circuit

Abstract

An automatic channel assignment circuit in a controlling association with an asynchronous or synchronous digital time division multiplexer and demultiplexer combination at one communication terminal to assign channels of transmitted and received synchronous data streams to asynchronous or synchronous source data signals in a manner to minimize temporary data memory regardless of the number of different bit rates of the source data signals by assigning the data signals to channels of the associated one of the transmitted and received data streams so that the bits of each of the data signals tend to have equal spacing throughout the bits of the associated one of the transmitted and received data streams. Each of the transmitted and received data streams have a predetermined fixed data format with respect to the channels and a given bit rate greater than the total of the bit rates of the source signals. However, the automatic channel assignment circuit provides, in effect, an automatically determined-at-the-time-of-rate-selection a variable data format with respect to the ports. The channel assignment control circuit also includes a means to automatically indicate when the total of the mixture of bit rates has exceeded an allowable maximum.