Multi-microprocessing unit on a single semiconductor chip

Abstract

This disclosure relates to a multimicroprocessor unit which is adapted for implementation in a single MOS semiconductor chip, which unit includes a plurality of sets of registers where each set represents a different processing capability. The unit further includes common elements which are shared by the different sets of registers in a time multiplex manner. The shared elements include two scratch pad memories, an arithmetic logic unit, and a control unit which incorporates a composite read only memory from which control signals are fetched to initiate the respective data transfers and arithmetic operations. This control memory acts as a decoder for encoded microinstructions retrieved from outside of the multi-processor unit. In this sense, the present invention employs both vertical and horizontal microprogramming as those terms are conventionally defined. The different sets of dedicated registers are formed of 4-bit shift registers so as to permit a four-way time slicing among the processing capabilities.