The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 1976
Filed:
Feb. 18, 1975
Edward C Hepworth, Apache Junction, AZ (US);
Rodney J Means, Tempe, AZ (US);
Motorola, Inc., Chicago, IL (US);
Abstract
An asynchronous interlock circuit for an interface adaptor circuit in a digital system includes a D-type latch, a D-type flip-flop, and an RS-type flip-flop interconnected to accept a peripheral status input from a peripheral equipment unit, a read status input and a read data input derived from control and selection inputs to the interface adaptor from a microprocessor unit of the digital system. The asynchronous interlock circuit stores information corresponding to a logical '1' on the peripheral status interrupt input in the D-type flip-flop, even if the latter signal disappears prior to acknowledgment by the microprocessor of a corresponding interrupt signal generated by the interface adaptor circuit. The D-type flip-flop is reset by a sequence of a read status signal and a read data signal, thereby avoiding problems which could arise if the peripheral status input remains at a logical '1' even after acknowledgment by the microprocessor unit of an interrupt signal generated by the interface adaptor. If a status change occurs on the peripheral status input while status is being read, the D-type latch is inhibited and the status change is not accepted until the read status operation is complete.