The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 07, 1976

Filed:

Jun. 30, 1975
Applicant:
Inventor:

Layton Balliet, Huntsville, AL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B / ;
U.S. Cl.
CPC ...
331 / ; 331 17 ;
Abstract

A phase-locked-loop circuit configuration is described which eliminates the statistical nature of the acquisition process, thereby improving or decreasing the acquisition or lock-up-time of the loop. The circuit configuration is such that given an input signal, that occurs at time T.sub.0, the loop error signal is reduced to a level where the lock-up-time is substantially reduced and predictable to a degree of certainty heretofore unattainable. In addition, by eliminating the statistical nature of the acquisition process, lock-up-time becomes a function of controllable system parameters, such as bandwidth, gain and circuit time constants.


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