The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 31, 1976

Filed:

Oct. 29, 1974
Applicant:
Inventors:

Heinz W Henninger, Uhlingen-Muhlhofen, DT;

Hans W Kiefer, NuBdorf, DT;

Lothar H Riethmuller, Uhldingen, DT;

Ernst Gunther Spreitzhofer, NuBdorf, DT;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06G / ; G06G / ;
U.S. Cl.
CPC ...
307229 ; 235183 ; 328127 ; 3403 / ;
Abstract

A integrator circuit is calibrated prior to measuring input signals therewith, by applying a reference voltage thereto with the output thereof applied to a comparator which has an output threshold set by a limit value signal proportional to the reference voltage. Clock pulses are accumulated by a counter until the comparator output threshold is reached and then a synchronizing means is actuated to simultaneously disconnect the reference voltage from the integrator and stop the counter, to reset the integrator, and to simultaneously connect the input signal to the integrator and the clock pulses to count down the accumulated count in the counter which thereby initiates the measuring mode. When the counter reaches zero, an output signal is produced which disconnects the input signal from the integrator to thereby stop the measuring mode. A frequency divider may be included to adjust the down counting frequency so that the integrating period of the measuring mode can be adjusted in proportion to the constant of integration that existed during the calibration mode.


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