The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 31, 1976
Filed:
Jun. 17, 1975
James Edward Lynch, Harrisburg, PA (US);
Kenneth Ronald Parmer, Harrisburg, PA (US);
Robert Franklin Cobaugh, Elizabethtown, PA (US);
AMP Incorporated, Harrisburg, PA (US);
Abstract
According to one aspect of the disclosure, a planar substrate receives a plurality of conductive posts therein, which posts include an offset medial portion having a laterally projecting notch portion. Certain posts are arranged with their notch portions in coplanar relationship and in latching registration with an interior sidewall portion of a housing received over the posts. Accordingly, the housing provides an insulating receptacle shroud for the posts and is latchingly retained in place without a need for attachment to the substrate. The shroud is also provided with card guides connected thereto by integral hinge portions enabling alignment of, and reducing twisting and warping of, the card guides. The card guides are additionally coupled together with rails further reducing twisting and warping of the guides. The terminals are advantageously mounted in strip form for ease in manufacture and assembly to the substrate. According to another aspect of the disclosure, a plurality of discrete electrically conductive posts are initially connected on selected center spacings to a common carrier strip without interconnecting portions between adjacent posts. A portion of the carrier strip is severed to separate a selected number of posts, which are inserted in a substrate. The carrier strip maintains the posts in alignment and in their desired center spacings. After the posts are secured to the substrate by reflow of a solder band provided on each post, the carrier strip is removed, allowing a connector housing to be slipped over the posts. The posts will interlock with the connector housing and positively anchor it to the substrate. In another embodiment, the connector housing is placed in registration on the substrate and the selected posts are then inserted simultaneously in the connector housing and in the substrate. When the solder bands of the posts are reflowed, the posts thus become secured to the substrate and simultaneously anchor the connector housing in positive location on the substrate. As in all the embodiments, the carrier strip connected to the posts is removed after solder reflowing. The disclosure further relates to a printed circuit board having mounted thereon a plurality of electrically conducting post-type contacts, enclosed by a removable electrically insulating housing latchably secured to a selected contact, and to a multi-layer printed circuit board and a method of fabrication thereof.