The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 1976

Filed:

Jun. 17, 1974
Applicant:
Inventor:

Bai-Cwo Feng, Wappingers Falls, NY (US);

Assignee:

IBM Corporation, Armonk, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B05D / ; B05D / ;
U.S. Cl.
CPC ...
156-8 ; 156 17 ; 427 93 ; 427 94 ; 427 96 ; 427259 ; 427271 ; 427273 ; 427331 ; 427335 ; 427336 ; 204192 ; 96 36 ; 96 362 ;
Abstract

An integrated circuit substrate surface, particularly a surface of electrically insulative material, having a pattern of elevated areas and a complementary pattern of unelevated areas is planarized by forming the photoresist pattern in registration with the pattern of unelevated areas, the photoresist pattern having narrower lateral dimensions than said elevated pattern whereby registration is facilitated, flowing the photoresist pattern to laterally expand the photoresist to cover and thereby mask the unelevated areas, and etching to lower the elevated areas which remain uncovered by the photoresist.


Find Patent Forward Citations

Feng, Bai-Cwo. (1976). Planarization of integrated circuit surfaces through selective (U.S. Patent No. 3976524). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/3976524

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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