The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 10, 1976

Filed:

Apr. 07, 1975
Applicant:
Inventors:

Huntington W Curtis, Chelsea, NY (US);

Roger L Verkuil, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
3401 / ; 307283 ; 3401 / ;
Abstract

A novel solid state device which exhibits two-terminal negative resistance characteristics. The negative resistance characteristic may be readily shaped by external bias control, providing a wide range of oscillatory or bistable properties. The negative resistance characteristic is obtained by a novel means of device operation exploiting an electron hole pair multiplication effect which is enhanced by high substrate doping in conjunction with appropriate biasing of the junctions within the device. The device exhibits a bias voltage controlled small signal negative resistance region, i.e., the device has a unique feature, a negative slope over an adjustable portion of its V-I characteristic. Bistable action is obtained with a single device. In the first stable state ('off') of the device, power dissipation is zero. In the second stable state ('on') of the device, power dissipation is adjustable to less than one micro-watt. One embodiment of the device is a novel and unobvious modification of a known N channel FET structure. The device may be readily fabricated by using large scale integration techniques well known in present day FET technology. The novel solid state device has utility in at least the following applications: (1) high density non-refresh memory; (2) gated latch (as three terminal device); (3) astable, monostable and bistable devices; (4) level detector, and (5) small signal (linear) oscillatory circuit.


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