The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 1976
Filed:
Sep. 29, 1975
Ernst Hebenstreit, Munich, DT;
Siemens Aktiengesellschaft, Berlin & Munich, DT;
Abstract
An integrated, programmable logic arrangement includes an AND matrix and an OR matrix which have individual gates. In the AND matrix each input is connected to a control line and via an inverter to another control line for production of a complementary input signal. A selector line and a base line are provided for each gate both in the AND matrix and in the OR matrix and the selector line is connectible to the supply potential. In the AND matrix, in programmed fashion, a switching transistor is provided at the intersection points between a control line and a selector line, or is not so provided, and a switching transistor so arranged at an intersection is connected by its gate terminal to an associated control line, Also, the switching transistor is connected, on the one hand, to an associated selector line of a gate and, on the other hand, to a base line which is connectible to another potential. The difference between the supply potential and the other potential corresponds to the supply voltage. In the OR matrix, in a correspondingly programmed fashion, a switching transistor is provided at an intersection point of a control line and a selector line or is not so provided. A switching transistor so provided is connected by its gate terminal to the associated control line and is connectible, on the one hand, to the selector line of a gate which may be connected to the supply potential and, on the other hand, to a base line which is connectible to ground. In the AND matrix a selector line of a gate is, in each case, connected by way of a pulsed load transistor to the supply potential and the base line of the gate is connectible by way of a pulsed cut-off transistor to the further potential. In the OR matrix, in corresponding fashion, a selector line of a gate is, in each case, connectible via a pulsed load transistor to the supply potential and the base line of the gate is connectible via a pulse cut-off transistor to the further potential. A pulsed flip-flop is arranged, in each case, between an output of the AND matrix and an input of the OR matrix and a pulsed flip-flop is provided, in each case, at an output of an OR matrix.