The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 20, 1976
Filed:
Aug. 14, 1975
William W Allen, Ambler, PA (US);
Herbert Stopper, Orchard Lake, MI (US);
Burroughs Corporation, Detroit, MI (US);
Abstract
An improved CML (Current Mode Logic) gate having voltage and temperature compensating means for maintaining output levels and input thresholds invariant with fluctations in supply voltage and junction temperature. The output of the compensating means, measured with respect to ground, will track variations in supply voltage on a one-to-one basis except that the output is allowed to vary by one V.sub.be with junction temperature. This output is supplied to the base of the constant-current source transistor which feeds the differential amplifier stage of the CML gate and to the base of a constant current source transistor whose collector is coupled to the base of the non-input transistor of the differential amplifier stage of the CML gate. The compensating circuitry includes an output transistor, resistive means for tracking variations in supply voltage, and a temperature compensation network having a temperature compensation factor of zero, both said resistive means and the output of said temperature compensation network are coupled to the base of the output transistor. The temperature compensation network achieves an overall compensation factor of zero by combining a temperature compensating subcircuit having a compensation factor of minus one with a temperature compensating subcircuit having a compensation factor of plus one via a unique voltage divider arrangement.