Central processor for a telephone exchange

Abstract

A central processor for controlling the operation of the subsystems of a telephone exchange switching system which are interconnected on a common data bus to establish requested service between telephone subscribers, wherein the exchange system includes a program memory also connected to the common data bus for storing a plurality of selectable multiple bit operational codes to be utilized by the central processor in response to a particular service being requested, a program address register for selecting a desired operational code from the program memory, an instruction register for storing the selected operational codes and a control word generator which provides function control signals in response to the particular operational codes stored in the instruction register. A bit time counter coupled to the control word generator controls the timing of the central processor so that the function control signals are supplied in proper time sequence. The central processor additionally includes an arithmetic logic unit which is responsive to the function control signals to perform the required logic and arithmetic functions as dictated by the selected operational code. Temporary stores are also provided and a bus address register provides storage of a particular address of a subsystem to receive the data produced by the arithmetic logic unit.