The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 1976
Filed:
Apr. 25, 1974
Pierre Marc Petroff, Westfield, NJ (US);
George Arthur Rozgonyi, Chatham, NJ (US);
Bell Telephone Laboratories, Incorporated, Murray Hill, NJ (US);
Abstract
Described is a procedure for virtually eliminating disclocations in multilayer structures of materials having a crystallographic zinc-blend structure, in particular quaternary layers of Al.sub.y Ga.sub.1.sub.-y As.sub.1.sub.-z P.sub.z grown on Al.sub.x Ga.sub.1.sub.-x As substrates (y > x .gtoreq. 0). By carefully controlling the quaternary layer thickness and the lattice parameter mismatch at the growth temperature, it is possible to change the direction of substrate dislocations as they enter the substrate/layer interface. The length of the dislocation in the interfacial plane can be extended so that it is 'infinitely' long, i.e., it reaches the edge of the wafer. As a result, the epitaxial quaternary layer and all layers subsequently grown thereon will be virtually dislocation free, provided that the thickness, stress and uniformity of the layers are such that no surface dislocation souces are activated. Also described are double heterostructure junction lasers with reduced values of both stress and dislocations.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile