The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 1976

Filed:

Feb. 10, 1975
Applicant:
Inventors:

Ury Priel, Cupertino, CA (US);

Robert A Anselmo, Canastota, NY (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307214 ; 307262 ; 307D / ;
Abstract

A dual inverter circuit wherein the first inverter circuit includes a pair of phase splitter transistors, one serving to feed the base of the pull-up transistor in the first inverter circuit and the other serving to feed the base of the phase splitter transistor in the second inverter circuit. The circuit provides a minimum delay time between the operation of the first inverter and the turn-on time of the second inverter while also providing active pull-up circuits, i.e., pull-up transistors, in the two inverters to insure fast operate times for both inverters especially desirable when feeding into large capacitance loads.


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