The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 1976

Filed:

Dec. 18, 1974
Applicant:
Inventor:

Frank Fellinger, Delaware, OH (US);

Assignee:

North Electric Company, Galion, OH (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L / ; H04L / ;
U.S. Cl.
CPC ...
178 / ; 325321 ;
Abstract

The data comprises 8-bit words, plus a leading bit as a start bit at a logic one, and a trailing bit for parity, for a total of 10 bits per group. A synchronizing circuit in the receiver selects a proper phase of clock signals for shifting the data bits into a shift register. An enable flip-flop for the synchronizing circuit is set in response to the start bit at the receiver input, and is reset when the start bit appears in the last bit position of the shift register. In a preferred embodiment, a clock signal is divided into three phases by a delay line. The synchronizing circuit has three flip-flops for selecting the phase when the enable flip-flop becomes set. These flip-flops enable gates for supplying the selected phase to the shift register. Delays are provided from the transmission line to the shift register and enable flip-flop inputs, so that the sampling is centered over each data bit.


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