Programmable logic controller with push down stack

Abstract

A programmable logic controller implemented in semiconductor integrated circuits which contains a memory for storing multi bit instructions and one bit data words with a processor selectively coupled to the memory for operating on the data in accordance with the instruction. A one bit word width push down stack is selectively connected to the processor for storing partial solutions to processor computations. The partial solutions are read from the stack in reverse order to entry thereof in response to completion of calculations of another part of the computations. The solution to the other part is combined with a partial solution retrieved from the push down stack.