The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 1976

Filed:

May. 06, 1975
Applicant:
Inventors:

Masataka Hirasawa, Yokohama, JA;

Akira Hashimoto, Yokohama, JA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; G08B / ;
U.S. Cl.
CPC ...
307205 ; 58 5 / ; 307209 ; 307270 ; 340336 ; 3501 / ;
Abstract

A logical circuit comprises a circuit having a plurality of insulated gate field effect transistors of different channel types and three terminals to which are connected corresponding voltage sources each having a different voltage level, and means for supplying first, second and third logical signals having the maximum and minimum voltage levels of the above-mentioned three different voltage levels to the circuit so that only one current path is always created between an output terminal of the circuit and any one of the three terminals. As a result, the logical circuit can generate an output having three logical levels.


Find Patent Forward Citations

Hirasawa, Masataka. (1976). Logical circuit for generating an output having three voltage levels (U.S. Patent No. 3949242). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/3949242

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…