The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 1976

Filed:

Sep. 03, 1974
Applicant:
Inventor:

Robert R Marley, Phoenix, AZ (US);

Assignee:

Motorola, Inc., Chicago, IL (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307218 ; 307215 ; 330 / ;
Abstract

A circuit for minimizing voltage excursions on the emitter-follower output terminals of an emitter coupled logic (ECL) gate including a compensating circuit connected to collector nodes associated with the input switching transistors and the reference switching transistor. The compensating circuit comprises a single current source for continuously delivering current which is selectively applied in predetermined amounts to one of the collector nodes residing in a high state. This predetermined amount of current compensates for undesired voltage changes experienced at the load impedance connected to that node due to varying ambient temperatures effecting the base-emitter junction of the output emitter follower transistor.


Find Patent Forward Citations

Marley, Robert. (1976). Fully compensated emitter coupled logic gate (U.S. Patent No. 3946246). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/3946246

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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