The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 02, 1976
Filed:
Sep. 03, 1974
Takayuki Yosioka, Hitachi, JA;
Tadashi Komada, Hitachi, JA;
Akira Sugano, Hitachi, JA;
Takafumi Fukumaru, Hitachi, JA;
Hitachi, Ltd., , JA;
Abstract
A proportional-integral circuit comprising a proportional element, an integrator and an adder. In an automatic mode, the proportional element delivers an output signal V.sub.P which is proportional to an input signal V.sub.i, the integrator delivers an output signal V.sub.I by integrating the input signal V.sub.i, and the adder delivers an output signal V.sub.PI which is the sum of the output V.sub.P of the proportional element and the output V.sub.I of the integrator. In a handling mode, the input signal V.sub.i is not applied to the integrator, and the output V.sub.P of the proportional element and an output V.sub.H of a manual handling source are applied to the integrator. A resistor is connected in parallel with a feedback capacitor in the integrator so that the integrator possesses an adding function. The adder adds up the output V.sub.P of the proportional element and the output V.sub.I of the integrator. Further, in this circuit, the gain of the integrator output V.sub.I relative to V.sub.P and V.sub.H is selected to be l/n, and the gain of the adder output V.sub.PI relative to V.sub.I is selected to be n.