The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 1976
Filed:
Aug. 27, 1974
Arthur Margolies, Framingham, MA (US);
GTE Laboratories Incorporated, Waltham, MA (US);
Abstract
An MOS circuit synchronizes an asynchronous input signal to first and second alternating clock pulses in an integrated circuit system employing clocked ratio logic. A bistable device, such as a flip-flop, has first and second complementary inputs for establishing the state of the device and an output reflecting the state of the device. An input circuit for the bistable device receives the asynchronous signal and applies the signal to the first complementary input and the inverted asynchronous signal to the second complementary input. In addition, the input circuit has gate logic, implemented with field effect transistors, which decouples the asynchronous input for all intervals of time except during the interval of the first clock pulse. An output circuit for the bistable device employs an inverter in series with a field effect transistor which is driven into condition only during the interval of the second clock pulse. The MOS synchronizer circuit thus insures that an output signal of usable logic level is generated for an input signal occuring at any time with respect to the clock pulses of a clocked ratio MOS system.