The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Jun. 24, 2024
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Christian Müller, Schweinfurt, DE;

Andressa Colvero Schittler, Niederense, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/685 (2026.01); H10W 70/692 (2026.01); H10W 72/00 (2026.01); H10W 74/10 (2026.01);
U.S. Cl.
CPC ...
H10W 90/401 (2026.01); H10W 70/685 (2026.01); H10W 90/701 (2026.01); H10W 70/692 (2026.01); H10W 72/884 (2026.01); H10W 74/10 (2026.01); H10W 74/114 (2026.01); H10W 90/00 (2026.01); H10W 90/734 (2026.01); H10W 90/754 (2026.01);
Abstract

A semiconductor module arrangement includes a first substrate with a first plurality of semiconductor bodies arranged thereon, a second substrate with a second plurality of semiconductor bodies arranged thereon, and a third substrate with a third plurality of semiconductor bodies arranged thereon. The first, second and third pluralities of semiconductor bodies together form a semiconductor arrangement, the semiconductor arrangement including a first node configured to be operatively coupled to a first electrical potential, and a second node configured to be operatively coupled to a second electrical potential that is different from the first electrical potential. A layout of the third substrate with the third plurality of semiconductor bodies arranged thereon equals a layout of the second substrate with the second plurality of semiconductor bodies arranged thereon. The first substrate is configured to be connected to the first node and the second node, and each of the second substrate and the third substrate is configured to be connected to a third node. A first current path extending between the first node and the third node via the first substrate and the second substrate provides identical voltage and current transfer characteristics as a second current path extending between the first node and the third node via the first substrate and the third substrate, and a third current path extending between the second node and the third node via the first substrate and the second substrate provides identical voltage and current transfer characteristics as a fourth current path extending between the second node and the third node via the first substrate and the third substrate.


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Müller, Christian. (2026). Semiconductor module arrangement (U.S. Patent No. 12796573). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12796573

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