The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Sep. 21, 2023
Applicant:

Semiconductor Components Industries, Llc, Scottsdale, AZ (US);

Inventors:

Jooyang Eom, Gimpo-si, KR;

Inpil Yoo, Unterhaching, DE;

Seungwon Im, Bucheon, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/60 (2026.01); H10W 40/25 (2026.01); H10W 70/63 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/614 (2026.01); H10W 40/255 (2026.01); H10W 70/611 (2026.01); H10W 70/635 (2026.01); H10W 74/111 (2026.01); H10W 90/00 (2026.01); H10W 90/734 (2026.01);
Abstract

In a general aspect, a semiconductor device assembly includes a first substrate including a first dielectric layer, and a first patterned metal layer disposed on a surface of the first dielectric layer. The assembly also includes a pre-molded semiconductor device module having a first side disposed on and electrically coupled with the first patterned metal layer, and a second substrate including a second dielectric layer, a second patterned metal layer disposed on a first surface of the second dielectric layer. The second patterned metal layer being is disposed on and electrically coupled with a second side of the module opposite the first side. The second substrate also includes a conductive via defined through the second dielectric layer. The conductive via electrically couples a signal terminal of the module with a patterned metal layer disposed on a second surface of the second dielectric layer opposite the first surface.


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Eom, Jooyang. (2026). Leadframe-less semiconductor device assemblies with dual-sided cooling (U.S. Patent No. 12796494). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12796494

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