Vertical power semiconductor device comprising source or emitter pad

Abstract

A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. A first wiring level is arranged over the first surface. The first wiring level includes a first lower source or emitter pad and a second lower source or emitter pad. A second wiring level is arranged over the first wiring level. The second wiring level includes a gate pad and a source or emitter pad. The source or emitter pad of the second wiring level is electrically connected to the first lower source or emitter pad and to the second lower source or emitter pad of the first wiring level. The first wiring level further includes a gate line laterally arranged between the first lower source or emitter pad and the second lower source or emitter pad. The gate line is vertically arranged between the source or emitter pad of the second wiring level and the first surface. The gate line is electrically insulated from the source or emitter pad of the second wiring level by an intermediate dielectric structure.