The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Sep. 08, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Chen-Fong Tsai, Hsinchu, TW;

Han-De Chen, Hsinchu, TW;

Chi On Chui, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/13 (2025.01); H10D 62/40 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10P 14/20 (2026.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/151 (2025.01); H10D 62/40 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10P 14/2926 (2026.01);
Abstract

A method includes: epitaxially growing a first multi-layer stack over a first substrate; epitaxially growing a second multi-layer stack over a second substrate; and bonding the first multi-layer stack to the second multi-layer stack. The first substrate and the second substrate have different crystalline orientations. The method further includes patterning the first multi-layer stack and the second multi-layer stack to form a fin, the fin comprising a plurality of lower nanostructures alternatingly stacked with first dummy nanostructures and a plurality of upper nanostructures alternatingly stacked with second dummy nanostructure; replacing the first dummy nanostructures with a first gate stack, the first gate stack surrounding each of the plurality of lower nanostructures; and replacing the second dummy nanostructures with a second gate stack, the second gate stack surrounding each of the plurality of upper nanostructures.


Find Patent Forward Citations

Quick Actions:

Tsai, Chen-Fong. (2026). Channel regions in stacked transistors and methods of forming the same (U.S. Patent No. 12796026). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12796026

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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