The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Nov. 09, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Ming He, San Jose, CA (US);

Mehdi Saremi, Danville, CA (US);

Rebecca Park, Mountain View, CA (US);

Muhammed Ahosan Ul Karim, San Jose, CA (US);

Harsono Simka, Saratoga, CA (US);

Sungil Park, Hwaseong-si, KR;

Myungil Kang, Hwaseong-si, KR;

Kyungho Kim, Hwaseong-si, KR;

Doyoung Choi, Hwaseong-si, KR;

Jaehyun Park, Hwaseong-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); H10D 30/01 (2025.01); H10D 30/83 (2025.01); H10D 62/17 (2025.01); H10D 62/85 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6219 (2025.01); H10D 30/0243 (2025.01); H10D 30/831 (2025.01); H10D 62/343 (2025.01); H10D 62/8503 (2025.01);
Abstract

Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a lower source/drain region of a 1polarity type connected to a lower channel structure; an upper source/drain region of a 2polarity type, connected to an upper channel structure, above the lower source/drain region; and a PN junction structure, between the lower source/drain region and the upper source/drain region, configured to electrically isolate the upper source/drain region from the lower source/drain region, wherein the PN junction structure includes a 1region of the 1polarity type and a 2region of the 2polarity type.


Find Patent Forward Citations

Quick Actions:

He, Ming. (2026). 3d stacked field-effect transistor device with pn junction structure (U.S. Patent No. 12795984). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12795984

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…