The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12795927 B1

Date of Patent:

Nov. 10, 2026

Filed:

Feb. 28, 2023

Memory device with sub-source layer

Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Won Geun Choi, Gyeonggi-do, KR;

Jung Shik Jang, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:

IP & T GROUP LLP

Primary Examiner:

William B Partridge

Assistant Examiner:

Gustavo G Ramallo

Int. Cl.

CPC ...

H10B 43/35 (2023.01); H10B 43/27 (2023.01);

U.S. Cl.

CPC ...

H10B 43/35 (2023.02); H10B 43/27 (2023.02);

Abstract

A memory device and a method of manufacturing the same. The memory device may include a stacked structure including a drain selection line, word lines, and a source selection line that are sequentially stacked, a main plug extending in a vertical direction of the stacked structure, and including a sub-source layer hole in a central portion of an upper area of the main plug, a separation pattern configured to separate the main plug in a vertical direction, and a source line stacked on the stacked structure, and configured to fill the sub-source layer hole.

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Choi, Won. (2026). Memory device with sub-source layer (U.S. Patent No. 12795927). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12795927

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