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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12795912 B1

PDFFull Text
Date of Patent:
Nov. 10, 2026

Filed:

Dec. 15, 2020

Memory device and manufacturing method thereof

Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Shunpei Yamazaki, Setagaya, JP;

Tetsuya Kakehata, Isehara, JP;

Yasuhiro Jinbo, Isehara, JP;

Yuji Egi, Atsugi, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Attorneys:

Eric J. Robinson

Robinson Intellectual Property Law Office, P.C.

Primary Examiner:

Sue A Purvis

Assistant Examiner:

Carnell undefined Hunter, III

Int. Cl.
CPC ...
H10B 41/35 (2023.01); G11C 16/04 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H10B 41/35 (2023.02); G11C 16/0483 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10D 30/6755 (2025.01);
Abstract

To provide a highly reliable memory device. A first insulator is formed over a substrate; a second insulator is formed over the first insulator; a third insulator is formed over the second insulator; an opening penetrating the first insulator, the second insulator, and the third insulator is formed; a fourth insulator is formed on the inner side of a side surface of the first insulator, a side surface of the second insulator, and a side surface of the third insulator, in the opening; an oxide semiconductor is formed on the inner side of the fourth insulator; the second insulator is removed; and a conductor is formed between the first insulator and the third insulator; and the fourth insulator is formed by performing, a plurality of times, a cycle including a first step of supplying a gas containing silicon and an oxidizing gas into a chamber where the substrate is placed, a second step of stopping the supply of the gas containing silicon into the chamber; and a third step of generating plasma containing the oxidizing gas in the chamber.

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Yamazaki, Shunpei. (2026). Memory device and manufacturing method thereof (U.S. Patent No. 12795912). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12795912

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