The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Oct. 31, 2023
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Manoj Mehrotra, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); H10B 10/18 (2023.02);
Abstract

Described examples include a semiconductor device having a first p-channel field effect transistor (p-FET). The first p-FET includes: a first gate dielectric layer on a surface of a substrate; a first gate structure on the first gate dielectric layer; and first silicon-germanium (SiGe) regions disposed in the substrate, on both sides of the first gate structure, the first SiGe regions extended to a first depth from the surface of the substrate. The semiconductor device also has a second p-FET. The second p-FET includes a second gate dielectric layer on the surface of the substrate; a second gate structure on the second gate dielectric layer; and second SiGe regions disposed in the substrate, on both sides of the second gate structure, the second SiGe regions extended to a second depth from the surface of the substrate, the second depth different than the first depth.


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Mehrotra, Manoj. (2026). Selective silicon-germanium process and structure (U.S. Patent No. 12795881). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12795881

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