Phase-locked loop circuit including a plurality of capacitor cell arrays with different capacitance changes and control method thereof

Abstract

A phase-locked loop (PLL) circuit comprising an oscillator including a first and a second capacitor cell array, each including a plurality of capacitor cells, and a control logic circuit connected to the oscillator. The control logic circuit configured to generate control code configured to control the oscillator such that the oscillator is configured to output a signal with a target frequency, the control code generated based on a first frequency of a first signal output from the oscillator and the target frequency, control at least some of capacitor cells included in the first capacitor cell array based on a first partial code generated based on a specified number of bits of the control code, and control at least some of capacitor cells included in the second capacitor cell array based on a second partial code generated based on bits other than the specified number of bits of the control code.