Polyphase filter for a dynamically reconfigurable oversampled channelizer

Abstract

Techniques are provided for a polyphase filtering in a dynamically reconfigurable two times (2×) oversampled channelizer. A polyphase filter implementing the techniques according to an embodiment includes a first plurality of dual port memory circuits and a multiplexer circuit configured to distribute input data for storage to the first plurality of dual port memory circuits. The polyphase filter also includes a second plurality of dual port memory circuits configured to store polyphase filter coefficients and a data alignment crossbar circuit configured to align the input data stored in the first plurality of dual port memory circuits with the polyphase filter coefficients stored in the second plurality of dual port memory circuits. The polyphase filter further includes a multiply circuit configured to perform multiplications of the aligned input data with the polyphase filter coefficients and an adder circuit to sum the results of the multiplications to generate a filtered output.