The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 2026
Filed:
Sep. 20, 2024
Ground fault circuit interrupter (gfci) with limit detection and adaptive sample accumulation window
Cypress Semiconductor Corporation, San Jose, CA (US);
Joseph Horanzy, Huntington Valley, PA (US);
Nidhin Mulangattil Sudhakaran, Unterhaching, DE;
Infineon Technologies Americas Corp., El Segundo, CA (US);
Abstract
An integrated circuit includes front-end circuitry coupled to a current sensor, which is coupled to alternating current (AC) mains, and to convert a leakage current to a converted voltage. An analog-to-digital converter (ADC), coupled to the front-end circuitry, converts the converted voltage to a digital signal. The ADC includes limit detection circuitry to detect the digital signal indicating the converted voltage is lower than a low threshold limit or higher than a high threshold limit and output a limit interrupt in response to the detection. Control logic is coupled to an output of the ADC and to process, in response to receiving the limit interrupt, the digital signal to determine a root mean square (RMS) value, and output a trip signal to trip logic to cause a disconnect of a current supplied to a load by the AC mains in response to the RMS value satisfying a threshold trip value.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile