The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Sep. 10, 2024
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Tatsuo Ogura, Yokkaichi Mie, JP;

Masaki Kondo, Yokkaichi Mie, JP;

Takashi Maeda, Kamakura Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); H10B 43/30 (2023.01); H10B 43/40 (2023.01); G11C 16/24 (2006.01); H10W 90/00 (2026.01); H10W 90/24 (2026.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); H10B 43/30 (2023.02); H10B 43/40 (2023.02); G11C 16/24 (2013.01); H10W 90/00 (2026.01); H10W 90/24 (2026.01);
Abstract

A semiconductor memory device includes: a first conductive layer; and a second conductive layer adjacent to the first conductive layer. Write loops each include: a first program operation that applies the first conductive layer with a program voltage and applies a bit line with a first bit line voltage; and a second program operation that applies the first conductive layer with the program voltage and applies the bit line with a second bit line voltage larger than the first bit line voltage. The write operation includes a state judging operation that judges whether a memory cell corresponding to the semiconductor layer and the second conductive layer has been controlled to a Low-state, or not. When the memory cell has been controlled to the Low-state, the first program operation is executed, and when the memory cell has not been controlled to the Low-state, the second program operation is executed.


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Ogura, Tatsuo. (2026). Semiconductor memory device (U.S. Patent No. 12793781). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12793781

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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