Timing control circuit and method for asynchronous time domain to synchronous time domain transfer and related memory module thereof

Abstract

A timing control circuit for use in a memory module includes: a clock generation circuit and a data queue. The clock generation circuit is configured to generate one or more delayed versions of an external clock signal and select one of the external clock signal and the one or more delayed versions of the external clock signal to generate a tracking clock signal according to a write latency count satisfaction indication signal and a row-to-column delay end indication signal. The data queue is configured to queue input data according to the external clock signal and generate an output data signal by de-queuing the queue data according to the tracking clock signal. Specifically, the output data signal and the tracking clock signal are utilized to perform a write operation within the memory module in response to an external write command.