The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Mar. 16, 2023
Applicant:

Drexel University, Philadelphia, PA (US);

Inventors:

Zhengfeng Wu, Philadelphia, PA (US);

Ioannis Savidis, Wallingford, PA (US);

Assignee:

Drexel University, Philadelphia, PA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/367 (2020.01); G06F 119/02 (2020.01);
U.S. Cl.
CPC ...
G06F 30/367 (2020.01); G06F 2119/02 (2020.01);
Abstract

A simulation-based optimization framework determines the sizing of components of an analog circuit to meet target design specifications while also satisfying the robustness specifications set by the designer. The robustness is guaranteed by setting a limit on the standard deviations of the variations in the performance parameters of a circuit across all process and temperature corners of interest. Classifier chains are used that, in addition to modeling the relationship between inputs and outputs, learn the relationships among output labels. Additional design knowledge is inferred from the optimal ordering of the classifier chain.


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Wu, Zhengfeng. (2026). Variation-aware analog circuit sizing with classifier chains (U.S. Patent No. 12792809). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12792809

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