Automatic blocking of unknown signals and grading of test point sites using untestable fault estimates to improve ic testability

Abstract

Systems, methods, architectures, mechanisms, tools, and apparatus providing design for testability (DFT) to rapidly estimate a number of faults made untestable by a given circuit signal being either in the X/Z logic state, uncontrollable, or unobservable, and to iteratively configure mechanisms for insertion of test point structure within a circuit under test (CUT) such as a digital circuit including a large number of sequential logic, combinational logic, latches, clocking/timing devices, and the like. Various embodiments contemplate several iterations to achieve a desired testing solution, illustratively (i) a first pass to eliminate uninitialized flip-flops and latches using blockers; (ii) a second pass to estimate the number of lost faults caused by each untestable site; and (iii) a final pass to select only the most essential test point sites using measures of Entropy, Entropy Gain, and/or Entropy Derivative. All three passes employ the novel tournament structure of this invention where test points compete with each other and are ranked by importance. For some circuits, it is also effective to combine these three main optimization functions with the level number of logic gates (their depth in the circuit).