Interconnect structures for configurable cpu pipelines

Abstract

A microprocessor to execute instructions and functions (defined as a macroprocessor) comprises a configurable CPU pipeline. Interconnect structures for configurable CPU pipelines are disclosed. In a first aspect, a configurable data router in an interconnect structure comprises a signal generation unit comprising configuration memory to dynamically receives a bit-code, decode and program configuration memory elements to generate a plurality of control signals to alter data bus coupling for pipelining. In a second aspect, a bit-byte configurable interconnect fabric blends bus-architectures of CPUs with bit-architectures of FPGAs for efficient heterogeneous computing. A bit-byte configurable interconnect fabric facilitates bus data flow between logic-blocks as well as bit-computing within logic-blocks, dramatically reducing the configuration memory required. In a third aspect, a configurable interconnect structure provides bit-stream configurability (at boot time) for user define content to execute in hardware as complex functions, and bit-code configurability (dynamically at run-time) to allow flexible sequencing of a plurality of complex functions to construct concatenated macro functions. In summary, the configurable interconnect structures provide the capability to dynamically program configurable CPU pipelines for a user defined application software content to execute in a custom hardware image.