Semiconductor package

Abstract

A semiconductor package includes a molded layer covering at least a portion of a chip structure and including a plurality of hollows in an upper surface thereof, an upper redistribution structure disposed on the molded layer and including a plurality of insulating layers and a plurality of upper redistribution layers respectively disposed on the plurality of insulating layers, and a plurality of posts penetrating through the molded layer and electrically connecting the lower redistribution layer to the plurality of upper redistribution layers, wherein the plurality of insulating layers include a first insulating layer between the first upper redistribution layer and the molded layer, and the first insulating layer includes a first sub-layer covering the upper surface of the molded layer and an upper surface of each of the plurality of posts and including protruding portions filling the plurality of hollows and openings exposing at least a portion of the upper surface of each of the plurality of posts, and a second sub-layer covering the first sub-layer and filling the openings, wherein a first height from the upper surface of the molded layer to an upper surface of the first sub-layer is less than a second height from the upper surface of the first sub-layer to an upper surface of the second sub-layer.