The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2026
Filed:
Jun. 18, 2024
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Assignee:
QUALCOMM INCORPORATED, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 20/41 (2026.01);
U.S. Cl.
CPC ...
H10W 90/701 (2026.01); H10W 20/427 (2026.01); H10W 20/435 (2026.01);
Abstract
A package comprising a substrate and a passive device coupled to the substrate through a plurality of solder interconnects. The substrate comprises at least one dielectric layer; and a plurality of interconnects. The passive device comprises a die substrate; a plurality of under bump metallization interconnects; and a plurality of pillar interconnects coupled to the plurality of under bump metallization interconnects, wherein at least one pillar interconnect comprises a wall pillar interconnect.
Quick Actions:
Chen, Yujen. (2026). Device comprising wall pillar interconnects (U.S. Patent No. 12787898). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787898
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile