The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Oct. 23, 2023
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventor:

Ákos Ferenc Hegedüs, Budapest, HU;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 72/00 (2026.01); H10W 72/50 (2026.01);
U.S. Cl.
CPC ...
H10W 90/701 (2026.01); H10W 70/611 (2026.01); H10W 70/65 (2026.01); H10W 72/50 (2026.01); H10W 90/00 (2026.01); H10W 72/884 (2026.01); H10W 90/734 (2026.01); H10W 90/753 (2026.01); H10W 90/754 (2026.01);
Abstract

A power semiconductor module arrangement includes: a housing; a substrate arranged in or forming a bottom of the housing, the substrate including a dielectric insulation layer and a first metallization layer attached to the dielectric insulation layer; a semiconductor arrangement on the substrate; and bus bars electrically coupled to each other by the semiconductor arrangement and/or the first metallization layer. Each bus bar has opposing first and second ends, a first surface having a first outline, and a second surface opposite the first surface, the second surface having a second outline that is a projection of the first outline. The first end of each bus bar is electrically and mechanically coupled to the substrate, the second end extending to the outside of the housing. The outline of the first surface of a bus bar is identical to the outline of the first surface of each of the other bus bars.


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Hegedüs, Ákos. (2026). Power semiconductor module arrangement (U.S. Patent No. 12787896). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787896

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